WILEY Journal Home Page
Papers under review through 2004
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Editorial | ||||||||
| Article Title | Special Issue: High Performance Agent Systems | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 1 | ||||||||
| Date | Jan 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.544 | ||||||||
| Article ID | CPE544 | ||||||||
| Author Name(s) | Omer F. Rana1David Kotz2 | ||||||||
| Author Email(s) | |||||||||
| Affiliation(s) | 1 2 | ||||||||
| Keyword(s) | |||||||||
Abstract |
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| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Dynamic configuration of access control for mobile components in FarGo | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 1 | ||||||||
| Date | Jan 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.545 | ||||||||
| Article ID | CPE545 | ||||||||
| Author Name(s) | Yoad Gidron1Israel Ben-Shaul2Ophir Holder3Yariv Aridor4 | ||||||||
| Author Email(s) | yariv@il.ibm.com4 | ||||||||
| Affiliation(s) | Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa, 32000, Israel 1 2 3 IBM Research Laboratory in Haifa, MATAM, 31905 Haifa, Israel 4 | ||||||||
| Keyword(s) | mobile components, dynamic layout, access control, FarGo, | ||||||||
Abstract |
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| Component mobility is an important enabling technology for the design of wide area pervasive applications, but it introduces new challenges in the critical aspect of access control. In particular, when mobility is used for dynamic relocation of distributed components, access from both remote and local mobile components needs to be uniformly controlled. The dynamic determination of execution location, possibly crossing multiple administrative authorities, requires dynamic establishment and enforcement of access control. The deployment over widely heterogeneous hosts and devices requires integration of access control with dynamic probing of resource availability so as to influence the relocation process. This paper presents a model for dynamic specification and enforcement of access control in the context of dynamically relocatable components, and an implementation in the Java-based FarGo framework. The specification follows a negotiation-based protocol that enables dynamic matching of available and required resources by providers and consumers, respectively. Enforcement is provided through a capability-based secure component reference architecture, which uniformly applies to both local and remote references, and through instance-level, as opposed to type-level (supported in Java), access control. Finally, access control is integrated into the programming model in a non-intrusive fashion, by separating the encoding of access control from the encoding of the logic of the application. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Performance investigation of an on-line auction system | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 1 | ||||||||
| Date | Jan 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.546 | ||||||||
| Article ID | CPE546 | ||||||||
| Author Name(s) | Jane Hillston1Leïla Kloul2 | ||||||||
| Author Email(s) | jeh@dcs.ed.ac.uk1 | ||||||||
| Affiliation(s) | LFCS, University of Edinburgh, Kings Buildings, Edinburgh EH9 3JZ, U.K. 1PRiSM, Université de Versailles, 45, Av. des Etats-Unis, 78035 Versailles Cedex, France 2 | ||||||||
| Keyword(s) | active networks, agent systems, electronic commerce, load balancing, stochastic process algebra, | ||||||||
Abstract |
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| The standard design of on-line auction systems places most of the computational load on the server and its adjacent links, resulting in a bottleneck in the system. In this paper, we investigate the impact, in terms of the performance of the server and its adjacent links, of introducing active nodes into the network. The performance study of the system is done using the stochastic process algebra formalism PEPA. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Fault-tolerant holonic manufacturing systems | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 1 | ||||||||
| Date | Jan 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.547 | ||||||||
| Article ID | CPE547 | ||||||||
| Author Name(s) | Martyn Fletcher1S. Misbah Deen2 | ||||||||
| Author Email(s) | deen@cs.keele.ac.uk2 | ||||||||
| Affiliation(s) | Data and Knowledge Engineering Group, Department of Computer Science, Keele University, Keele, Staffordshire ST5 5BG, U.K. 1 2 | ||||||||
| Keyword(s) | fault-tolerance, agent-based manufacturing, holonic manufacturing, | ||||||||
Abstract |
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| This paper presents a model of fault-tolerant holonic manufacturing systems (HMS) where each holon"s activities are controlled by an intelligent software agent. Multiple agents schedule actions, resolve conflicts and manage information to produce, transport, assemble, inspect and store customized products. Our model provides robustness and distribution transparency across a shop-floor where unpredictable failures occur with machines, control software and communication networks. Each autonomous holon is composed of a hierarchy of large-grain functional components where interaction is carried out by user-defined cooperation strategies. These strategies enable holons to coordinate their behaviour through exchanging messages and sensing/actuating of their shared environment. Therefore, holonic agents can select suitable rescheduling and recovery mechanisms to tolerate faults and keep the manufacturing system working. We also propose how the IEC 1499 standard (Function Block Architecture) for distributed control systems could be used to implement our model. The model presented here is a crystallization of some abstract concepts from a generic cooperating agent system, with suitable extensions to meet the criteria of the ongoing HMS project. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Which paradigm should I use? An analytical comparison of the client-server, remote evaluation and mobile agent paradigms | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 1 | ||||||||
| Date | Jan 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.548 | ||||||||
| Article ID | CPE548 | ||||||||
| Author Name(s) | Antonio Puliafito1Salvatore Riccobene2Marco Scarpa3 | ||||||||
| Author Email(s) | apulia@ingegneria.unime.it1 | ||||||||
| Affiliation(s) | Dipartimento di Matematica - Contrada Papardo, S. Speroni, 98166 Messina, Italy 1Dipartimento di Matematica - V. le A. Doria 6, 95125, Catania, Italy 2Istituto di Informatica e Telecomunicazioni - V. le A. Doria 6, 95125, Catania, Italy 3 | ||||||||
| Keyword(s) | client-server, remote evaluation, mobile agents, performance analysis, Petri nets, | ||||||||
Abstract |
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| In this paper we deal with the study of the actual convenience of using the agent programming paradigm for accesssing distributed service. We try to point out the benefits of such a communication paradigm, by providing an analytical study of its basic features in comparison with the client-server approach and remote evaluation. The aim of the paper is to show how the Petri net analysis technique can be used for deciding whether to use traditional client/server, remote evaluation or mobile agents paradigm in designing a particular evaluation. So, we present several models of non-Markovian Petri nets, which have been solved through the WebSPN tool, and we provide a close comparison between the agents technique, the client-server and the remote evaluation communication paradigm. The results that we have obtained show how agents must not always be considered the only solution to any communication issue, since in several cases their use might even reveal a drawback. We also focus out attention on providing some practical remarks, which can help the developer during the design in order to select the communication paradigm which best suits the features of the application that has to be developed. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Editorial | ||||||||
| Article Title | Editorial: Concurrency and Computation: Practice and Experience | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 1 | ||||||||
| Date | Jan 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.582 | ||||||||
| Article ID | CPE582 | ||||||||
| Author Name(s) | Geoffrey C. Fox1Anthony J. G. Hey2 | ||||||||
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| Affiliation(s) | 1 2 | ||||||||
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Abstract |
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| No abstract | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | A parallel Viterbi decoding algorithm | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 2 | ||||||||
| Date | Feb 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.539 | ||||||||
| Article ID | CPE539 | ||||||||
| Author Name(s) | J. S. Reeve1 | ||||||||
| Author Email(s) | jsr@ecs.soton.ac.uk1 | ||||||||
| Affiliation(s) | Department of Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, U.K. 1 | ||||||||
| Keyword(s) | trellis decoding, Viterbi decoding, BCH codes, | ||||||||
Abstract |
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| In this paper we express the Viterbi algorithm as a matrix-vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array. We describe the algorithm for Bose-Chaudhuri-Hocquenghem (BCH) codes which have a task graph with its valence restricted to four inputs and four outputs. The method is also applicable to convolution codes, but the complexity of the task graph increases with the number of input bits for these codes. Results for BCH codes are given for two general purpose parallel machines, an IBM SP2 and a Meiko CS2. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Emmerald: a fast matrix-matrix multiply using Intel"s SSE instructions | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 2 | ||||||||
| Date | Feb 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.549 | ||||||||
| Article ID | CPE549 | ||||||||
| Author Name(s) | Douglas Aberdeen1Jonathan Baxter2 | ||||||||
| Author Email(s) | daa@csl.anu.edu.au1 | ||||||||
| Affiliation(s) | Research School of Information Sciences and Engineering, Australian National University, Canberra, Australia 1 2 | ||||||||
| Keyword(s) | GEMM, SIMD, SSE, matrix multiply, deep memory hierarchy, | ||||||||
Abstract |
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| Generalized matrix-matrix multiplication forms the kernel of many mathematical algorithms, hence a faster matrix-matrix multiply immediately benefits these algorithms. In this paper we implement efficient matrix multiplication for large matrices using the Intel Pentium single instruction multiple data (SIMD) floating point architecture. The main difficulty with the Pentium and other commodity processors is the need to efficiently utilize the cache hierarchy, particularly given the growing gap between main-memory and CPU clock speeds. We give a detailed description of the register allocation, Level 1 and Level 2 cache blocking strategies that yield the best performance for the Pentium III family. Our results demonstrate an average performance of 2.09 times faster than the leading public domain matrix-matrix multiply routines and comparable performance with Intel"s SIMD small matrix-matrix multiply routines. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Experiences from integrating algorithmic and systemic load balancing strategies | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 2 | ||||||||
| Date | Feb 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.550 | ||||||||
| Article ID | CPE550 | ||||||||
| Author Name(s) | Ioana Banicescu1Sheikh Ghafoor2Vijay Velusamy3Samuel H. Russ4Mark Bilderback5 | ||||||||
| Author Email(s) | ioana@erc.msstate.edu1 | ||||||||
| Affiliation(s) | Mississippi State University, Department of Computer Science, NSF Engineering Research Center for Computational Field Simulation, MS 39762, U.S.A. 1 2 3 4 5 | ||||||||
| Keyword(s) | load balancing, dynamic scheduling, resource management, parallel applications, distributed runtime environment, | ||||||||
Abstract |
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| Load balancing increases the efficient use of existing resources for parallel and distributed applications. At a coarse level of granularity, advances in runtime systems for parallel programs have been proposed in order to control available resources as efficiently as possible by utilizing idle resources and using task migration. Simultaneously, at a finer granularity level, advances in algorithmic strategies for dynamically balancing computational loads by data redistribution have been proposed in order to respond to variations in processor performance during the execution of a given parallel application. Combining strategies from each level of granularity can result in a system which delivers advantages of both. The resulting integration is systemic in nature and transfers the responsibility of efficient resource utilization from the application programmer to the runtime system. This paper presents the design and implementation of a system that combines an algorithmic fine-grained data parallel load balancing strategy with a systemic coarse-grained task-parallel load balancing strategy, and reports on recent experimental results of running a computationally intensive scientific application under this integrated system. The experimental results indicate that a distributed runtime environment which combines both task and data migration can provide performance advantages with little overhead. It also presents proposals for performance enhancements of the implementation, as well as future explorations for effective resource management. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Analysis and measurement of the effect of kernel locks in SMP systems | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 2 | ||||||||
| Date | Feb 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.551 | ||||||||
| Article ID | CPE551 | ||||||||
| Author Name(s) | Akihiro Kaieda1Yasuichi Nakayama2Atsuhiro Tanaka3Takashi Horikawa4Toshiyasu Kurasugi5Issei Kino6 | ||||||||
| Author Email(s) | yasu@cs.uec.ac.jp2 | ||||||||
| Affiliation(s) | Department of Computer Science, The University of Electro-Communications, Chofu, Tokyo 182-8585, Japan 1 2 NEC Corporation, Kawasaki 216-8555, Japan 3 4 5 6 | ||||||||
| Keyword(s) | SMP systems, operating systems, parallel programs, performance evaluation, kernel lock, | ||||||||
Abstract |
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| This article reports the use of case studies to evaluate the performance degradation caused by the kernel-level lock. We define the lock ratio as a ratio of the execution time for critical sections to the total execution time of a parallel program. The kernel-level lock ratio determines how effective programs work on symmetric multiprocessor (SMP) systems. We have measured the lock ratios and the performance of three types of parallel programs on SMP systems with Linux 2.0: matrix multiplication, parallel make, and WWW server programs. Experimental results show that the higher the lock ratio of parallel programs, the worse their performance becomes. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Parallel solvers for discrete-time algebric Riccati equations | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 2 | ||||||||
| Date | Feb 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.552 | ||||||||
| Article ID | CPE552 | ||||||||
| Author Name(s) | Rafael Mayo1Enrique S. Quintana-Ortí2Gregorio Quintana-Ortí3Vicente Hernández4 | ||||||||
| Author Email(s) | quintana@inf.uji.es2 | ||||||||
| Affiliation(s) | Depto. de Informática, Universidad Jaume I, 12080-Castellón, Spain 1 2 3 Depto. de Sistemas Informáticos y Computación, Universidad Politécnica de Valencia, 46071-Valencia, Spain 4 | ||||||||
| Keyword(s) | algebraic Riccati equations, Stein equations, linear control systems, parallel algorithms and architectures, | ||||||||
Abstract |
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| We investigate the numerical solution of discrete-time algebraic Riccati equations on a parallel distributed architecture. Our solvers obtain an initial solution of the Riccati equation via the disc function method, and then refine this solution using Newton"s method. The Smith iteration is employed to solve the Stein equation that arises at each step of Newton"s method. The numerical experiments on an Intel Pentium-II cluster, connected via a Myrinet switch, report the performance and scalability of the new algorithms. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | A parallel Navier-Stokes solver for the rotating flow problem | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 3 | ||||||||
| Date | March 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.554 | ||||||||
| Article ID | CPE554 | ||||||||
| Author Name(s) | Rudnei Dias da Cunha1Álvaro Luiz de Bortoli2 | ||||||||
| Author Email(s) | rudnei@mat.ufrgs.br1 | ||||||||
| Affiliation(s) | Postgraduate Programme on Applied Mathematics, Institute of Mathematics, Federal University of Rio Grande do Sul, Brazil 1 2 | ||||||||
| Keyword(s) | parallel computing, message-passing, computational fluid dynamics, | ||||||||
Abstract |
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| In this paper, we investigate the parallel solution of rotating internal flow problems, using the Navier-Stokes equations as proposed by Speziale and Thangam (in 1983) and Speziale (in 1985). A Runge-Kutta time-stepping scheme was applied to the equations and both sequential and message-passing implementations were developed, the latter using MPI, and were tested on a four-processor SGI Origin200 distributed, global shared memory parallel computer and on a 32-processor IBM 9076 SP/2 distributed memory parallel computer. The results show that our approach to parallelize the sequential implementation requires little effort whilst providing good results even for medium-sized problems. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Using knowledge-based systems for research on parallelizing compilers | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 3 | ||||||||
| Date | March 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.563 | ||||||||
| Article ID | CPE563 | ||||||||
| Author Name(s) | Chao-Tung Yang1Shian-Shyong Tseng2Yun-Woei Fann3Ting-Ku Tsai4Ming-Huei Hsieh5Cheng-Tien Wu6 | ||||||||
| Author Email(s) | ctyang@nspo.gov.tw1 | ||||||||
| Affiliation(s) | Ground System Section, National Space Program Office, 8F, No. 9 Prosperity 1st Road, Science-Based Industrial Park, Hsinchu, Taiwan 300, ROC 1Department of Computer&Information Science, National Chiao Tung University, Hsinchu, Taiwan 300, ROC 2 3 4 5 6 | ||||||||
| Keyword(s) | parallelizing compiler, knowledge-based system, loop parallelization, multithreaded OS, program restructuring, | ||||||||
Abstract |
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| The main function of parallelizing compilers is to analyze sequential programs, in particular the loop structure, to detect hidden parallelism and automatically restructure sequential programs into parallel subtasks that are executed on a multiprocessor. This article describes the design and implementation of an efficient parallelizing compiler to parallelize loops and achieve high speedup rates on multiprocessor systems. It is well known that the execution efficiency of a loop can be enhanced if the loop is executed in parallel or partially parallel, such as in a DOALL or DOACROSS loop. This article also reviews a practical parallel loop detector (PPD) that is implemented in our PFPC on finding the parallelism in loops. The PPD can extract the potential DOALL and DOACROSS loops in a program by verifying array subscripts. In addition, a new model by using knowledge-based approach is proposed to exploit more loop parallelisms in this paper. The knowledge-based approach integrates existing loop transformations and loop scheduling algorithms to make good use of their ability to extract loop parallelisms. Two rule-based systems, called the KPLT and IPLS, are then developed using repertory grid analysis and attribute-ordering tables respectively, to construct the knowledge bases. These systems can choose an appropriate transform and loop schedule, and then apply the resulting methods to perform loop parallelization and obtain a high speedup rate. For example, the IPLS system can choose an appropriate loop schedule for running on multiprocessor systems. Finally, a runtime technique based on the inspector/executor scheme is proposed in this article for finding available parallelism on loops. Our inspector can determine the wavefronts of a loop with any complex indirected array-indexing pattern by building a DEF-USE table. The inspector is fully parallel without any synchronization. Experimental results show that the new method can resolve any complex data dependence patterns where no previous research can. One of the ultimate goals is to construct a high-performance and portable FORTRAN parallelizing compiler on shared-memory multiprocessors. We believe that our research may provide more insight into the development of a high-performance parallelizing compiler. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Redistribution strategies for portable parallel FFT: a case study | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 3 | ||||||||
| Date | March 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.564 | ||||||||
| Article ID | CPE564 | ||||||||
| Author Name(s) | Anshu Dubey1Daniele Tessera2 | ||||||||
| Author Email(s) | dubey@tagore.uchicago.edu1 | ||||||||
| Affiliation(s) | Astronomy&Astrophysics, University of Chicago, 5640 S. Ellis Ave., Chicago, IL 60637, U.S.A. 1Dipartimento di Informatica e Sistemistica, Università degli Studi di Pavia, I-27100 Pavia, Italy 2 | ||||||||
| Keyword(s) | FFT, distributed transpose, MPI; communication policy, | ||||||||
Abstract |
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| The best approach to parallelize multidimensional FFT algorithms has long been under debate. Distributed transposes are widely used, but they also vary in communication policies and hence performance. In this work we analyze the impact of different redistribution strategies on the performance of parallel FFT, on various machine architectures. We found that some redistribution strategies were consistently superior, while some others were unexpectedly inferior. An in-depth investigation into the reasons for this behavior is included in this work. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | A distributed implementation of a virtual machine for Java | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 3 | ||||||||
| Date | March 1 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.565 | ||||||||
| Article ID | CPE565 | ||||||||
| Author Name(s) | Yariv Aridor1Michael Factor2Avi Teperman3 | ||||||||
| Author Email(s) | teperman@il.ibm.com3 | ||||||||
| Affiliation(s) | IBM Haifa Research Laboratory, Matam, Advanced Technology Center, Haifa 31905, Israel 1 2 3 | ||||||||
| Keyword(s) | cluster machine, Java, objects, Java Virtual Machine, single system image, | ||||||||
Abstract |
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| The cluster virtual machine (VM) for Java provides a single system image of a traditional Java Virtual Machine (JVM) while executing in a distributed fashion on the nodes of a cluster. The cluster VM for Java virtualizes the cluster, supporting any pure Java application without requiring that application be tailored specifically for it. The aim of our cluster VM is to obtain improved scalability for a class of Java Server Applications by distributing the application"s work among the cluster"s computing resources. The implementation of the cluster VM for Java is based on a novel object model which distinguishes between an application"s view of an object (e.g. every object is a unique data structure) and its implementation (e.g. objects may have consistent replications on different nodes). This enables us to exploit knowledge on the use of individual objects to improve performance (e.g. using object replications to increase locality of access to objects). We have already completed a prototype that runs pure Java applications on a cluster of NT workstations connected by a Myrinet fast switch. The prototype provides a single system image to applications, distributing the application"s threads and objects over the cluster. We used the cluster VM to run, without change, a real Java Server Application containing over 10 Kloc1Kloc means Kilo lines of code-used to describe the size of applications in terms of source lines count. for the source code and achieved high scalability for it on a cluster. We also achieved linear speedup for another application with a large number of independent threads. This paper discusses the architecture and implementation of the cluster VM. It focuses on achieving a single system image for a traditional JVM on a cluster while describing, in short, how we aim to obtain scalability. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Object-oriented analysis and design of the Message Passing Interface | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 4 | ||||||||
| Date | Apr 10 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.556 | ||||||||
| Article ID | CPE556 | ||||||||
| Author Name(s) | Anthony Skjellum1Diane G. Wooley2Ziyang Lu3Michael Wolf4Purushotham V. Bangalore5Andrew Lumsdaine6Jeffrey M. Squyres7Brian McCandless8 | ||||||||
| Author Email(s) | tony@cs.msstate.edu1 | ||||||||
| Affiliation(s) | Engineering Research Center and Department of Computer Science, Mississippi State University, Mississippi State, MS 39762, U.S.A. 1 2 3 4 5 Laboratory for Scientific Computing, Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN 46556, U.S.A. 6 7 8 | ||||||||
| Keyword(s) | message passing, parallel programming, object-oriented application programmer interface, design patterns, MPI-1, MPI-2, | ||||||||
Abstract |
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| The major contribution of this paper is the application of modern analysis techniques to the important Message Passing Interface standard, work done in order to obtain information useful in designing both application programmer interfaces for object-oriented languages, and message passing systems. Recognition of ‘Design Patterns’ within MPI is an important discernment of this work. A further contribution is a comparative discussion of the design and evolution of three actual object-oriented designs for the Message Passing Interface ( MPI-1SF ) application programmer interface (API), two of which have influenced the standardization of C++ explicit parallel programming with MPI-2, and which strongly indicate the value of a priori object-oriented design and analysis of such APIs. Knowledge of design patterns is assumed herein. Discussion provided here includes systems developed at Mississippi State University (MPI++), the University of Notre Dame (OOMPI), and the merger of these systems that results in a standard binding within the MPI-2 standard. Commentary concerning additional opportunities for further object-oriented analysis and design of message passing systems and APIs, such as MPI-2 and MPI/RT, are mentioned in conclusion. Connection of modern software design and engineering principles to high performance computing programming approaches is a new and important further contribution of this work. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Object Systems Paper | ||||||||
| Article Title | Strong types for coordinating active objects | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 4 | ||||||||
| Date | Apr 10 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.570 | ||||||||
| Article ID | CPE570 | ||||||||
| Author Name(s) | Franz Puntigam1 | ||||||||
| Author Email(s) | franz@complang.tuwien.ac.at1 | ||||||||
| Affiliation(s) | Technische Universität Wien, Institut für Computersprachen, Argentinierstraße 8, A-1040 Vienna, Austria 1 | ||||||||
| Keyword(s) | type systems, concurrent programming languages, active objects, | ||||||||
Abstract |
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| An object type is usually regarded as a contract between an object and each of its clients. However, in concurrent (and sometimes also in sequential) systems it is more useful to regard a type as a contract between an object and the set of all clients: when the object acts as a shared resource, the clients must be coordinated before sending messages to the object. Process types of active objects specify constraints on the ordering of messages. Static type checking ensures proper coordination of clients so that objects receive messages only in acceptable orderings. As presented in this article, the process type system is based on a simple computation model where active objects communicate via asynchronous message passing. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK | ||||||||
| Category | Research Article | ||||||||
| Article Title | Algorithmic support for model transformation in object-oriented software development | ||||||||
| Volume ID | 13 | ||||||||
| Issue ID | 5 | ||||||||
| Date | Apr 25 2001 | ||||||||
| DOI(URI) | http://dx.doi.org/10.1002/cpe.555 | ||||||||
| Article ID | CPE555 | ||||||||
| Author Name(s) | Siegfried Schönberger1Rudolf K. Keller2Ismail Khriss3 | ||||||||
| Author Email(s) | schoenbe@iro.umontreal.ca1 | ||||||||
| Affiliation(s) | Département d"informatique et de recherche opérationelle, Université de Montréal, C.P. 6128, succursale Centre-ville, Montréal, Québec H3C 3JZ, Canada 1 2 3 | ||||||||
| Keyword(s) | object-oriented analysis and design, model transformation, transformation algorithm, Unified Modeling Language (UML), collaboration diagram, state transition diagram, | ||||||||
Abstract |
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| Current methods for object-oriented software development provide notation for the specification of models, yet do not sufficiently relate the different model types to each other, nor do they provide support for transformations from one model type to another. This makes transformations a manual activity, which increases the risk of inconsistencies among models and may lead to a loss of information. We have developed and implemented an algorithm supporting one of the transitions from analysis to design, the transformation of scenario models into behavior models. This algorithm supports the Unified Modelling Language (UML), mapping the UML"s collaboration diagrams into state transition diagrams. We believe that CASE tools implementing such algorithms will be highly beneficial in object-oriented software development. In this paper, we provide an overview of our algorithm and discuss all its major steps. The algorithm is detailed in semi-formal English and illustrated with a number of examples. Furthermore, the algorithm is assessed from different perspectives, such as scope and role in the overall development process, issues in the design of the algorithm, complexity, implementation and experimentation, and related work. Copyright © 2001 John Wiley & Sons, Ltd. | |||||||||
| Publisher | John Wiley & Sons, Ltd. Chichester, UK |
| Category | Research Article |
| Article Title | A new parallel domain decomposition method for the adaptive finite element solution of elliptic partial differential equations |
| Volume ID | 13 |
| Issue ID | 5 |
| Date | Apr 25 2001 |
| DOI(URI) | http://dx.doi.org/10.1002/cpe.569 |
| Article ID | CPE569 |
| Author Name(s) | Randolph E. Bank1Peter K. Jimack2 |
| Author Email(s) | |
| Affiliation(s) | Department of Mathematics, University of California at San Diego, La Jolla, CA 92093, U.S.A. 1School of Computing, University of Leeds, Leeds LS2 9JT, U.K. 2 |